The present invention relates to a transistor circuit and, more particularly, to a peak/bottom level hold circuit comprising of insulated gate field effect transistors (called hereinafter "MOS transistors").
A level hold circuit is widely employed in an electronic system to detect and hold the level or amplitude of a signal voltage. Such circuit is composed of a MOS transistor and a capacitor in general.
Referring to FIG. 1, a peak hold circuit according to a prior art includes an N-channel MOS transistor Q1 and a capacitor C connected in series between a first power line Vcc and a second, ground power line GND. A resistor R is connected in parallel to the capacitor C. The transistor Q1 has a threshold voltage of substantially zero (0 v). An input signal voltage Vin is supplied to the gate of the transistor Q1, and a voltage across the capacitor C is derived as an output voltage Vout.
In such a construction, when the input voltage Vin is larger than the output voltage Vout, the transistor Q1 is turned ON to charge the capacitor C. The output voltage Vout is thereby made large. When the input voltage Vin becomes smaller than the output voltage Vout, the transistor Q1 is turned OFF. The capacitor C is thereby discharged through the resistor R to lower the output voltage Vout. Thus, the output voltage Vout varies as shown by a doted line in FIG. 2 in response to change in level of the input voltage Vin indicated by a solid line. That is, this circuit functions as a peak level hold circuit.
However, the cycle period of the input voltage Vin is not always constant, but sometimes changes as shown in FIG. 3. In that case, a certain peak level as indicated by a reference numeral 10 or 11 in FIG. 3 is not detected by the circuit shown in FIG. 1. Moreover, when the cycle period of the input voltage Vin is prolonged, the peak level represented by the output voltage Vout is not held, but discharged to the ground level.